verilog学习笔记（verilog部分基础语法）

verilog学习笔记（verilog部分基础语法）022）将结果打印输出到控制台：比如$display(“%b” a);是直接将结果输出到控制台，$mointor($time ”%b” c);可以实时监控数据的变化。01仿真结果1）可以直接看波形：使用仿真软件比如modelsim将电路逻辑的代码文件和激励文件加入工程进行编译和仿真即可。

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本文介绍仿真中testbench的编写，如果有错误的地方，欢迎指出，感谢。

简介

首先贴一个激励文件的图片先大致看一下：用来验证串口接收数据。testbench用来产生激励来验证电路的正确性，不需要可综合，以reg类型作为模块的输入激励，以wire型接收模块的输出。

01

仿真结果

1）可以直接看波形：使用仿真软件比如modelsim将电路逻辑的代码文件和激励文件加入工程进行编译和仿真即可。

2）将结果打印输出到控制台：比如$display(“%b” a);是直接将结果输出到控制台，$mointor($time ”%b” c);可以实时监控数据的变化。

02

系统任务

$display和$write均用来输出结果，区别在于$display输出后会自动换行，$write不会

$mointor和$strobe均可以用来输出和监控值，区别在于$strobe是在本时刻所有的赋值语句完成后才进行打印的，而$mointor会立刻在本时刻进行打印。

$time和$realtime均可返回当前的仿真的时刻，区别在于$time是以64位整数值的形式返回时间的，$realtime是以实数的形式返回的。

$finish和$stop均可用于对仿真的时间的控制，$finish会在执行到此时结束仿真，$stop会在执行到此时中断暂停仿真。

$random产生一个32位带符号的随机数，$random%a会得到在1-b~b-1范围内的整数。

03

延时语句

阻塞型和非阻塞型：阻塞型会从initial开始计时，然后依次延时 #4 a=1;非阻塞型是从initial开始各个延时同时开始，#4 a<=1;#5 b<=2;是在4单位长度时间后对a进行赋值，然后1个单位时间后对b进行赋值。

04

触发事件

边沿触发：@事件，事件包括posedge(上升沿)，negedge(下降沿)，信号(包括上升沿和下降沿)

电平触发：wait(信号在某个电平)执行操作。

05

任务和函数

任务：task 端口 begin end endtask在模块内进行定义，然后在模块中调用:任务名(端口)，可以在多次重复同一个操作时调用任务减少代码量，但是任务里面不能出现initial和always过程块。

函数：function 位宽或者类型 函数名 输入信号 begin end endfunction

其中的类型有：integer：整数型 real:实数型 函数名相当于一个寄存器，在函数内部可以将返回值存到这个寄存器中，在调用时和任务的调用一样，区别在于任务只能用于过程块，函数可以用于过程块和赋值语句。

06

模块延时

模块延时：对模块从一个输入引脚到一个输出引脚的延时进行定义。

specify specparam定义常量 (输入端口=>输出端口)=延时时长 endspecify

specparam和parameter一样是用来定义的常量的，不同在于specaram是仅在模块延时中，parameter在外部。在specify中可以调用一些系统函数来检查时序是否正确，比如$setup(被检查的信号，参考的信号，规定的产生一次被检查信号所产生参考信号的最少数目)。

07

仿真时间标度

仿真时间标度：`timescale 单位/精度 比如截图中的表示#time中time是1ns的整数倍，且能够表示的最小时间单位是1ns。

英文翻译✦

Writing testbench

This article introduces the preparation of the testbench in the simulation. The author is also a beginner. If there are mistakes please point out thank you.

Introduction: The testbench is used to generate excitation to verify the correctness of the circuit. It does not need to be synthesizable. The reg type is used as the input excitation of the module and the output of the module is received by the wire type.

First paste a picture of the incentive file to take a general look: used to verify that the serial port receives data

Simulation results:

1) You can directly see the waveform: Use simulation software such as modelsim to add the code file and excitation file of the circuit logic to the project for compilation and simulation.

2) Print the result to the console: for example $display("%b" a); directly outputs the result to the console $mointor($time "%b" c); can monitor the data in real time Variety.

System tasks:

Both $display and $write are used to output the result the difference is that $display will automatically wrap after output $write will not

Both $mointor and $strobe can be used to output and monitor values. The difference is that $strobe is printed after all assignment statements at this moment are completed while $mointor will be printed immediately at this moment.

Both $time and $realtime can return the current simulation time the difference is that $time returns the time in the form of a 64-bit integer value and $realtime returns the time in the form of a real number.

Both $finish and $stop can be used to control the time of the simulation. $finish will end the simulation when it is executed and $stop will interrupt the simulation when it is executed.

$random generates a 32-bit signed random number $random%a will get an integer in the range 1-b~b-1.

Delay statement:

Blocking type and non-blocking type: The blocking type will start timing from the initial and then delay in turn #4 a=1; the non-blocking type will start each delay from the initial at the same time #4 a<=1; #5 b< =2; is to assign a value to a after 4 units of time and then assign a value to b after 1 unit of time.

Trigger event: edge trigger: @ event events include posedge (rising edge) negedge (falling edge) signal (including rising edge and falling edge)

Level-triggered: wait (the signal is at a certain level) to perform an operation.

Tasks and functions:

Task: task port begin end endtask is defined in the module and then called in the module: task name (port) the task can be called when the same operation is repeated many times to reduce the amount of code but the initial and always process blocks cannot appear in the task .

Function: function bit width or type function name input signal begin end endfunction

The types are: integer: integer real: real function name is equivalent to a register the return value can be stored in this register inside the function and the call is the same as the call of the task the difference is that the task can only be used for the process Blocks functions can be used in procedural blocks and assignment statements.

Module Delay: Define the delay of the module from an input pin to an output pin.

specify specparam definition constant (input port => output port) = delay time endspecify

Specparam and parameter are used to define constants the difference is that specaram is only in module delay and parameter is external. Some system functions can be called in specify to check whether the timing is correct such as $setup (checked signal reference signal the minimum number of reference signals generated by the specified generation of the checked signal at one time).

Simulation time scale: `timescale unit/precision For example in the screenshot time in #time is an integer multiple of 1ns and the minimum time unit that can be represented is 1ns.

参考资料:《verilog数字系统设计教程》夏宇闻著

翻译：谷歌翻译

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