emmc分为几种（eMMC深入浅出第六章）

emmc分为几种（eMMC深入浅出第六章）Two push pull I/O cannot be connected together as in this mode the ‘0’ and ‘1’ are both strong once connected together either output uncertain voltage level or even damage the I/O in the worst case. Open Drain I/O This is very useful when there is more than one eMMC device is connected on the eMMC bus. This is also the reason that open drain mode is used only on the CMD line in Card Identificat

Section 2 Signal Integrity第二节 信号完整性

Before we start this topic we need first understand two kinds of I/O open drain mode and push pull mode.

我们今天来谈SI话题。在我们开始这个话题之前，我们需要先理解两种I/O，漏极开路模式和推挽模式。

When we look into the IC (Integrated Circuit) the open drain I/O is a single MOSFET usually type N. the source is connected to GND（Ground） while drain is left floated as output this is why it is called open drain. When the MOSFET switch is on the output will be low ‘0’ as drain is connected with source GND. While the switch is off the output will become float. Then we need a pull up resistor on the output either internal the IC or external on the PCB to give a fixed voltage high ‘1’.

当我们往IC（集成电路）里面看，漏极开路I/O是一个单独的MOS管，通常是N型。源极连接到GND (地)，而漏极作为输出浮空，这是为什么称为漏极开路的原因。当这个MOS管开关开通的时候，因为漏极连接到源极GND所以输出为低’0’。当开关关闭的时候，输出悬空。所以我们需要一个不论是在IC内部或者外部在PCB的输出上的上拉电阻来给出一个固定的高电平‘1’。

Push pull I/O is much popular. The difference from open drain I/O is that it is composed by a pair of MOSFET one N type the other one is P type. The drain of both MOSFET are connected together but the source of P type MOSFET is connected to VDD the source of N type MOSFET is connected to GND. In this I/O mode only one switch will be on at a time to output either ‘1’ or ‘0’ based on the control gate input. This is quite like the pedals of the bICycle to provide continuous force moving forward. It is where the name push pull come from.

推挽I/O更加常见一些。跟漏极开路不同的是由一对MOS管组成，一个是N型，一个是P型。两个MOS管的漏极连在一起，但是P型MOS管的源极接到VDD，N型MOS管的源极接到GND。在这个I/O模式下，根据栅极的输入一次只会有一个开关开通输出‘1’或是‘0’。这个就非常像自行车的两个踏板提供不断前进的动力。这个也即是推挽这个名字的来历。

Push pull is more popular and more powerful to output a digital high ‘1’ or a digital low ‘0’ then why we still need open drain? To figure out this we need introduce one advantage of the open drain I/O wired-AND logic. Wired-AND allows multiple drain connected together. If one of the drain is connected to GND the bus voltage level will be low voltage ‘0’. The pull up resistor will act as a key factor to undertake the electric potential difference between VDD and non-open MOSFET drain. This drain should be high voltage ‘1’ but forced to low voltage ‘0’ .

推挽更加常见也更加强劲有力地输出数字高电平‘1’或者数字低电平‘0’。那么为什么我们还需要漏极开路？为了搞清楚这个，我们需要介绍漏极开路的一个优点，线与逻辑。线与允许在多个漏极连在一起。如果其中有一个漏极连接到了GND，总线电压电平就是低电平‘0’。上拉电阻起到了一个关键作用来承受没有打开开关的那些MOS管漏极和VDD之间的电势差。而这个漏极本来应该是高电平‘1’，但是却被强制拉到低电平‘0’。

Two push pull I/O cannot be connected together as in this mode the ‘0’ and ‘1’ are both strong once connected together either output uncertain voltage level or even damage the I/O in the worst case. Open Drain I/O This is very useful when there is more than one eMMC device is connected on the eMMC bus. This is also the reason that open drain mode is used only on the CMD line in Card Identification Mode. Once the dedicated eMMC is selected with the RCA and enters the Data Transfer mode all the I/O including CLK DATA CMD will be in powerful push pull mode that could drive heavier loading.

两个推挽的I/O不能连在一起，因为在这个模式下，’0’或者’1’都太强了。一旦接在一起，要不就输出一个不确定电平，甚至是最坏情况下损坏I/O。漏极开路I/O在eMMC总线上连接有多个eMMC器件时非常有用。这个也是漏极开路模式只用在卡识别模式里的命令线。一旦特定eMMC一旦通过RCA选定进入数据传输模式，包括时钟，数据，命令线在内的所有的I/O都会用更加强劲有力的能驱动更重负载的推挽模式。

When we talk about the digital signal we need understand what is the criteria for the digital ‘1’ and ‘0’. eMMC specification has different definition of High and Low for the Input and output signal separately. Below we take the example of the definition of I/O voltage level of 1.8V VCCQ from eMMC Specification.

当我们说到数字信号，我们需要知道数字‘1’和‘0’的标准。eMMC规范对于输入和输出的高低电平信号分别有不同的定义。以下我们用eMMC规范的1.8伏 VCCQ的I/O电平定义为例。

We use 1.8V to represent the VCCQ with the range of 1.70V to 1.95V as 1.8V is the typical value and easier for us to calculate and demonstrate. Then according to the specification for the eMMC device output voltage level below 0.45V is considered to be digital ‘0’ voltage level above 1.35V (1.8V-0.45V) is considered to be digital ‘1’. Any voltage level between 0.45V to 1.35V is an undefined eMMC output voltage level and it could not be expected this undefined signal to be recognized correctly by Host receiver. This will cause Host receiver confusion and bit error in communication channel.

我们用1.8伏来表示1.7伏到1.95伏的范围，因为1.8伏是典型值而且比较容易计算和解释。根据规范，对于eMMC器件输出，低于0.45伏的电平被认为是数字‘0’，高于1.35伏（1.8伏-0.45伏）的电平被认为是数字‘1’。任何在0.45伏和1.35伏之间的电平被认为是未定义的eMMC输出电平，所以我们不能期望主机接收端正确识别这个未定义电平。这会引起主机接收端紊乱以及信道误码。

The same is on the eMMC input the High voltage level ‘1’ is within the range 1.17V (0.65x1.8V) to 2.1V (1.8V 0.3V) the Low voltage level ‘0’ is within the range -0.3V (GND-0.3V) to 0.63V (0.35x1.8V). Any voltage level between 0.63V to 1.17V on the eMMC input is also undefined voltage level and could not be correctly recognized by the eMMC receiver.

eMMC的输入也是一样，高电平‘1’是在1.17伏（0.68x1.8伏）到2.1伏（1.8伏 0.3伏）的范围之内，低电平‘0’是在-0.3伏（地电平-0.3伏）到0.63伏（0.35x1.8伏）的范围之内。任何在0.63伏到1.17伏之间的eMMC输入电平为未知电平而不能被eMMC接收端正确识别。

In order to get the correct signal voltage level value we need measure the signals as close as possible to the receiver we call it near end measurement. For example if we need to understand the eMMC device output signal integrity we need to choose a test point as close as possible to Host receiver. Vice versa for the eMMC device input signal we need choose a test point as close as possible to eMMC device receiver. Thus we could get more accurate measurement result. But theoretically we can never reach the real receiver inside the IC for the measurement even in some case we can only get the far end test point this is the reason why the simulation is much more important than measurement to understand if there is real SI issue in the design.

为了得到正确的信号电平值，我们需要尽可能在接收端测量，我们称之为近点测量。比如，如果我们需要了解eMMC器件输出信号完整性，我们需要尽可能靠近主机接收端选择测量点。与之相反，对于eMMC器件的输入信号我们需要尽可能靠近eMMC器件接收端选择测试点。这样我们才能得到更加准确的测量结果。但是理论上我们永远也无法在IC内部的真正的接收端测量，甚至在某些场合下我们只能得到远端测量点，这也是为什么通过仿真比测量来了解是否有SI问题更加重要。

We are going to talk about the signal input to eMMC device today. The two key input timings are Input set-up time and Input hold time. Setup time is the minimum amount of time the data signal should be held steady before the clock event so that the data is reliably sampled by the clock. Hold time is the minimum amount of time the data should be held after the clock event so that the data are reliably sampled.

我们今天来聊eMMC器件的输入信号。两个重要的输入时序是输入建立时间和输入保持时间。建立时间是在时钟事件之前数据信号需要保持稳定的最少时间从而依据时钟信号可以可靠地采样。保持时间是在时钟事件之后数据信号需要保持稳定的最少时间从而依据时钟信号可以可靠地采样。

From the definition we could know that both these two timings are for reliably input data sampling by the receiver in the synchronous digital system. The time is relative to the clock edge in the eMMC specification. If in the SDR mode then only rising edge of the clock is used for the sampling so we have one pair of the Input set-up time and Input hold time. If in the DDR mode then both rising and falling edge of clock are used for the sampling then we have two pairs of Input set-up time and Input hold time. The purpose of the minimum amount time requirement for both Input set-up time and Input hold time is to give enough margin for the eMMC device for sampling correct data.

从定义来看我们可以知道这两个时序都是为了在同步数字系统里接收端可以可靠数据采样输入数据。这个时间在eMMC规范里面是相对于时钟沿来说的。如果是在SDR模式，只用时钟的上升沿采样数据，所以我们有一对输入建立时间和输入保持时间。如果是在DDR模式，时钟的上升沿和下降沿都会被用来采样数据，我们就有两对输入建立时间和输入保持时间。最小时间要求的目的是为了输入建立时间和输入保持时间都能给出足够的裕量给eMMC器件正确采样数据。

The request timing for input clock is as stable as possible stable means less distortion and better duty cycle closed to 50%. In order to achieve such kind of timing request eMMC specification defines the minimum pulse width of both high and low cycle in the clock signal and also the maximum accumulated distortion in the clock signal to avoid marginal issue when sampling by clock edges. Clock frequency should not exceed 200Mhz. Although we do see the clock frequency sometimes cross this 200Mhz criteria without any issue but it only because the 200Mhz frequency is not that high and sampling timing margin could still compensate a little bit in some cases hence it really better to follow the maximum 200Mhz criteria.

输入时钟的时序要求是尽可能的稳，稳意味着更少的偏离和更好地接近50%的占空比。为了达到这样的时序要求 eMMC规范定义了最小的时钟的高电平周期和低电平周期的脉冲宽度以及累计的最大时钟偏离来避免时钟边沿采样时候的裕量不够的问题。

The general requirement for the eMMC device input and output signal are slew rate. In the digital world the most ideal waveform is square wave. But in the real world this could never be achieved we can only expect rising or falling time of the digital signal edges as fast as possible to minimize the side effect to sampling during the signal transition time. Slew rate is defined as ratio of the time and voltage transition between maximum low voltage level ‘0’ to minimal High voltage level ‘1’ the unit is V/ns.

eMMC输入信号和输出信号的通用要求是斜率。在数字世界里，最理想的波形是方波。但是现实世界这个永远不可能达到，我们只能期望数字信号的边沿上升或者下降时间越快越好，从而减少由于信号切换时间而引起的采样的副作用。斜率被定义成时间和电压在低电平‘0’和高电平‘1’之间切换的比值，单位是伏每纳秒。

Today we are going to talk about the eMMC device output timing. It is somehow a little bit more complex than eMMC device input timing. The reason is the synchronizing clock. For the eMMC device input timing synchronizing clock is always the same direction as the input signals it will be easier for the host to ensure the input timing to eMMC device although there might be minor delay difference between the input signals and clock. But for the eMMC device output timing clock is the opposite direction with the output signals the delay caused by Jitter or Skew of the output signal lines and clock could not be neglected any more. This is why there are a few output-timing scenarios.

今天我们来聊聊eMMC器件输出的时序。这个比eMMC器件的输入的时序要复杂一些。原因是同步时钟。对于eMMC器件的输入时序，同步时钟总是和输入信号同一个方向，主机会容易保证向eMMC器件的输入时序，尽管输入信号和时钟之间存在一些微小的延时差异。但是对于eMMC器件的输出时序，时钟和输出信号是反方向的，由于输出信号以及时钟的抖动或者偏差引起的延时不能再被忽视了。

For the legacy speed timing with clock frequency lower than 26Mhz scenario since the frequency is low the timing impact caused by the opposite direction of clock and signals is minor. eMMC device output-timing requirement is quite like eMMC device input-timing requirement. There are also output setup time and output hold time just like the input setup time and input hold time.

对于低于26MHz时钟的传统速度时序场景，因为频率低，时钟和信号相反引起的时序影响非常小。eMMC器件输出时序的要求和eMMC器件的输入时序的要求类似。也会有输出建立时间和输出保持时间，就像输入建立时间和输入保持时间一样。

For the high-speed timing with clock frequency lower than 52Mhz scenario one more timing requirement is added to check the output signals delay time with the last clock cycle. We need start to take care of impact caused by the opposite direction of clock and output signals since the frequency is higher. Especially for the DDR mode we need check output signals delay time to the corresponding rising edge or falling edge of the last clock cycle.

对于时钟低于52Mhz的高速时序场景，增加了一个时序的要求去检查输出信号和上一个时钟周期的延时。因为频率更高了，我们需要开始关心时钟和输出信号反向带来的影响。特别是对于DDR模式，我们需要检查输出信号相对应的上个时钟周期的上升沿或者下降沿。

For the higher HS200 timing SDR sampling with clock frequency up to 200Mhz scenario host sampling point could not be simply considered as the clock edge any more. Thus tuning mechanism is added. What eMMC device output-timing requirement is to guarantee the reliable sampling range for host called valid window. Tuning mechanism will help host to find a best sampling point in this valid windows. There is also a maximum time requirement of output delay to the nearest clock prior of data in valid windows called phase difference in HS200.

对于更高的HS200时序，时钟最高到200Mhz的SDR采样的场景，主机的采样点不能再简单地认为是时钟的边沿。因此加入了tuning机制。eMMC器件输出时序要求是确保给主机一个可靠的采样范围，称为有效窗口。Tuning机制会帮助主机在有效窗口里找到一个最佳的采样点。也还有一个相对于在有效窗口里的数据之前的最近一个时钟的时延的最大时间要求，在HS200里面成为相位差异。

The unit in HS200 is also different from the low frequency using time as unit is not accurate enough as the clock period could be small and not fixed (up to 200Mhz means 100Mhz or 150Mhz are also allowed). UI (unit interval) is introduced as the unit for the HS200 timing to cover different clock frequency. Temperature factor is also introduced in the HS200 timing as the drift of the high-speed signals under high temperature or low temperature need be considered seriously as well.

HS200时序下的单位也跟低频用的不同，因为时钟周期会很小而且不固定（最大200Mhz意味着100Mhz或者150Mhz都可以）所以用时间作为单位不够准确了。引入UI（单元间隔）作为HS200时序的单位可以覆盖不同的时钟频率。因为高速信号在高温和低温下的漂移同样需要被慎重考虑，因此温度因素也在HS200被引入。

For the last and most critical HS400 timing DDR sampling with clock frequency up to 200Mhz scenario even tuning could not 100% guarantee the host correct sampling then a special data strobe signal added also called as RCLK which is sent from eMMC device and has got the same direction as other output signals. It is the ultimate solution to resolve the direction difference between clock and output signals. The frequency of output Data Strobe is the same as input clock the purpose is to give host the synchronized allowable sampling range which cover the output data valid window. What’s more the Data Strobe of enhanced strobe mode will even help for the output response on the command line. The only thing need be noted is the skew between the Data Strobe and output signals as the frequency is high.

对于最后一个和最严峻的HS400时序，时钟最高达200Mhz的DDR采样的场景，甚至是tuning也不能100%保证主机的正确采样，然后引入了一个特殊的数据选通信号，也被叫做RCLK，由eMMC器件发出和其他输出信号同一个方向。这是解决时钟和输出信号方向不同的终极解决方案。输出数据选通的频率和输入时钟是一样的，作用是给主机一个覆盖输出数据的有效窗口的同步的允许的采样点范围。更进一步，增强的选通模式的数据选通甚至可以帮助命令线上的应答输出。唯一需要注意的是因为频率高因此数据选通和输出信号之间的偏差。

The standalone requirement of the DS is quite like clock also need to check the if frequency exceeding 200Mhz or not and minimum pulse width of High voltage level and Low voltage level cycle. The difference of the DS from clock is that it will be seen only when output signals so the minimal pre-amble and minimum post-amble time of DS is defined to make sure DS is stable when needed.

DS的单独的要求和时钟的一样，同样需要检查主频超出最大的200Mhz没有，以及高电平和低电平的最小脉宽。和时钟不一样的是，DS只会在有输出信号时才有，所以定义了DS的最小的前导和后导来保证DS需要时是稳定的。