verilog常用语法（verilog部分基础语法）

小君 2023-07-13 04:33:19 426

verilog常用语法（verilog部分基础语法）寄存器类型：表示一个数据存储单元，只能在always和initial语句中被赋值，赋值相当于改变的就是触发器存储的值。其一般为无符号数，当赋值为负数时会自动转换为补码形式。寄存器类型，参数类型线网类型各个模块连接其他的模块的连线就是线网类型，未连接时为高阻态，常用的为wire型，常用来表示用以assign关键字指定的组合逻辑信号，比如wire [7:0] a定义了一个8位的wire型数据，且wire a=b&c和wire a;assign a=b&c;等价。02

本文整理部分verilog HDL的基础语法，如果有错误的地方，欢迎指出，感谢。

verilog常用语法（verilog部分基础语法）(1)

三种数据类型

线网类型

各个模块连接其他的模块的连线就是线网类型，未连接时为高阻态，常用的为wire型，常用来表示用以assign关键字指定的组合逻辑信号，比如wire [7:0] a定义了一个8位的wire型数据，且wire a=b&c和wire a;assign a=b&c;等价。

寄存器类型，参数类型

寄存器类型：表示一个数据存储单元，只能在always和initial语句中被赋值，赋值相当于改变的就是触发器存储的值。其一般为无符号数，当赋值为负数时会自动转换为补码形式。

定义：reg 寄存器位宽寄存器个数变量名称列表 reg [7:0] mem[127:0] reg1 reg2;128个8位寄存器和名为reg1 reg2的两个8位寄存器。

参数类型：定义一个常数，parameter p=0;

数值运算符及表达式

数值：1，0，不定状态x 高阻态z

整数及表示： /-’ 位宽基数符号（b o d h）数字如4’b1x01表示4位二进制

运算符和表达式：大致和C语言相同，注：

1) ===(全等)，&(按位与) &&(逻辑与)，^(异或)，^~(同或) |(按位逻辑或) ||(逻辑或)

2) 算数操作中结果的位宽由长的位宽决定，赋值语句中由左端决定，多的部分高位舍弃

3) 几个和C语言不同的，{信号1的某几位，信号2的某几位}位拼接运算符，c=&b缩减运算符，这句表示的是从b的第一位和第二位与之后和第三位与并依次进行直到得到了一位二进制

程序设计和描述方式

数据流建模

连续赋值语句：其目标类型为标量线网(wire a)和向量线网(wire [2:0] a)，连续赋值语句为并行语句，分为显式赋值语句(eg:wire [3:0] a;assign #10 a=b&c)和隐式赋值语句(eg:wire [3:0] a=c|b)

行为级建模

1）过程语句

(1)initial begin ... end相当于是复位后开始执行的部分

(2)always@(<敏感事件列表>)满足条件就执行的部分，在程序执行的过程中一直会检测是否满足条件。

对过程语句使用的注意：

1)使用过程对组合电路进行描述时，所有的输入信号都要写入敏感事件表中

2)对时序电路需要时间信号和部分输入信号写入敏感事件表

2）语句块：

串行语句块(begin-end)和并行语句块(fork-join) 就是其中的语句按照串行或并行的方式执行

结构化建模

1) 模块级：引用模块: (1)模块名实例名（端口名列表）对应信号名和端口名的顺序不能变 (2)模块名实例名 (.端口名n(信号名n))

2) 门级：使用内置的门电路定义门结构，比如and And(out in1 in2 in3)定义了一个三输入的与门

3) 开关级：MOS开关和双向开关，和门级类似使用语法类似，但使用的关键字不同

阻塞与非阻塞

过程赋值语句：阻塞性过程赋值语句(变量=表达式)和非阻塞性过程赋值语句(变量<=表达式)。

区别：阻塞赋值就是串行过程，非阻塞赋值就是并行过程，一般在组合逻辑中使用阻塞赋值，在时序中使用非阻塞，二者在对应电路上的区别:eg:begin a=b;d=a; end对应的就是一个D触发器，begin a<=b;d<=a; end对应的就是两个D触发器，非阻塞是同时计算右式，阻塞是顺序执行

条件分支和循环语句

条件分支语句：if-else语句和C语言相同，case-endcase多用于多条件译码电路(注：需要列举出所有情况，多的要用default)

循环语句：

1)forever 引导语句块表示永久循环直到遇到系统任务$finish

2) repeat(循环次数)语句块

3)while和for和C语言相同

英语翻译

This article organizes some basic grammars of verilog HDL. The author is a beginner. If there are mistakes please point out thank you.

Three data types: net type register type parameter type

Wire net type: The connection of each module to other modules is the wire net type. When it is not connected it is in a high-impedance state. The commonly used wire type is used to represent the combinational logic signal specified by the assign keyword such as wire [7 :0] a defines an 8-bit wire type data and wire a=b&c and wire a;assign a=b&c; are equivalent.

Register type: Represents a data storage unit which can only be assigned in always and initial statements. Assignment is equivalent to changing the value stored in the trigger. It is generally an unsigned number and it is automatically converted to complement form when it is assigned a negative number.

Definition: reg register bit width number of registers Variable name list reg [7:0] mem[127:0] reg1 reg2; 128 8-bit registers and two 8-bit registers named reg1 reg2.

Parameter type: define a constant parameter p=0;

Value: 1 0 indeterminate state x high impedance state z

Integer and representation: /-’ bit width radix symbol (b o d h) number such as 4’b1x01 means 4-bit binary

operators and expressions: roughly the same as the C language note:

1) === (congruent) & (bitwise and) && (logical and) ^ (exclusive or) ^~ (exclusive or) | (bitwise logical or) || (logical or)

2) The bit width of the result in the arithmetic operation is determined by the bit width of the length. The left end of the assignment statement is determined and the more high bits are discarded.

3) Several different from the C language {some bits of signal 1 some bits of signal 2} bit splicing operator c=&b reduction operator this sentence means from the first bit and the first bit of b. After the two-bit and and the third-bit and and and in turn until a binary is obtained

Program design and description:

Data flow modeling:

1) Continuous assignment statement: its target types are scalar wire net (wire a) and vector wire net (wire [2:0] a). Continuous assignment statements are parallel statements which are divided into explicit assignment statements (eg: wire [3] :0] a;assign #10 a=b&c) and implicit assignment statements (eg:wire [3:0] a=c|b)

Behavioral Modeling:

1) Procedure statement:

(1)initial begin ... end is equivalent to the part that starts to execute after reset

(2) always@() The part that is executed when the condition is met will always check whether the condition is met during the execution of the program

Notes on the use of procedure statements: 1) When using procedure to describe combinational circuits all input signals must be written into the sensitive event table

2) Write the sensitive event table for sequential circuits requiring time signals and some input signals

Statement block: serial statement block (begin-end) and parallel statement block (fork-join) that is the statements in it are executed in a serial or parallel manner

Procedure assignment statement: blocking procedure assignment statement (variable = expression) and non-blocking procedure assignment statement (variable <= expression)

Blocking assignment is a serial process and non-blocking assignment is a parallel process. Generally blocking assignment is used in combinational logic and non-blocking is used in timing. The difference between the two in the corresponding circuit: eg:begin a=b;d=a; end corresponds to a D flip-flop begin a<=b;d<=a; end corresponds to two D flip-flops non-blocking is to calculate the right formula at the same time blocking is sequential execution

Conditional branch statement: if-else statement is the same as C language case-endcase is mostly used in multi-conditional decoding circuits (Note: all cases need to be listed and default is used for many)

Loop statement: 1) The forever bootstrap statement block represents a permanent loop until the system task $finish is encountered

4) repeat (number of loops) statement block 3) while and for are the same as C language

Structured Modeling:

1) Module level: Reference module: (1) Module name instance name (list of port names) The order of the corresponding signal name and port name cannot be changed (2) Module name instance name (. port name n (signal name n))

2) Gate level: use the built-in gate circuit to define the gate structure such as and And(out in1 in2 in3) defines a three-input AND gate

3) Switch level: MOS switch and bidirectional switch similar to the gate level the syntax is similar but the keywords used are different

verilog常用语法（verilog部分基础语法）(2)